ST72324 datasheet(158/161 Pages) STMICROELECTRONICS

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ST72324

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15.3 FLASH REV “X” and ALL ROM DEVICES

15.3.1 Read-out protection with LVD

The LVD is not supported if the read-out protection

is enabled.

15.3.2 External clock source with PLL

External clock source is not supported with the

PLL enabled.

15.3.3 I/O Port A and F Configuration

When using an external quartz crystal or ceramic

resonator, the fOSC2 clock may be disturbed be-

cause the device goes into reserved mode control-

led by Port A and F.

This happens with either one of the following con-

figurations:

PA3=0, PF4=1, PF1=0 while CSS and PLL op-

tions are both disabled and PF0 is toggling

PA3=0, PF4=1, PF1=0, PF0=1 while CSS or PLL

options are enabled

This is detailed in the following table:

As a consequence, for cycle-accurate operations,

these configurations are prohibited in either input

or output mode.

Workaround:

To avoid this occurring, it is recommended to con-

nect one of these pins to GND (PF4 or PF0) or

VDD (PA3 or PF1).

15.3.4 LVD Operation

Depending on the operating conditions, especially

the VDD ramp up speed and ambient temperature,

in some cases the LVD may not start. When this

occurs, the MCU may operate outside the guaran-

teed functional area (see datasheet Figure 76)

without being forced into reset state.

In this case, proper use of the watchdog may

make it possible to recover through a watchdog re-

set and allow normal operations to resume.

Consequently, the LVD function is not guaranteed

in the current silicon revision. For complete securi-

ty, an external reset circuit must be added.

15.4 ALL ROM DEVICES

15.4.1 AVD not supported

On some devices with a specific VDD ramp up

speed the AVD may not start. As a result it cannot

generate interrupts when VDD rises and falls.

15.4.2 Internal RC oscillator operation

Internal RC oscillator operation is not supported in

ROM devices.

CSS PLL PA3 PF4 PF1 PF0

Clock

Disturbance

OFF OFF

Tog

glin

Max. 2 clock

cycles lost at

each rising or

falling edge of

PF0

xON

Max. 1 clock

cycle lost out

of every 16

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