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ST72260G датащи(PDF) 147 Page - STMicroelectronics |
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ST72260G датащи(HTML) 147 Page - STMicroelectronics |
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147 / 171 page ![]() ST72260G, ST72262G, ST72264G 147/171 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40 to +85°C unless otherwise specified Figure 99. Typical Application with RESET pin 6)7)8) Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 4. The reset network protects the device against parasitic resets. 5. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 6. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 13.9.1 . Otherwise the reset will not be taken into account internally. 7. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 13.2.2 on page 123. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage 0.16xVDD V VIH Input high level voltage 0.85xVDD Vhys Schmitt trigger voltage hysteresis1) 2.5 V VOL Output low level voltage 2) VDD=5V IIO=+5mA 0.68 0.95 V IIO=+2mA 0.28 0.45 RON Pull-up equivalent resistor VDD=5V 20 40 80 k Ω VDD=3V 85 tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time 4) 20 µs tg(RSTL)in Filtered glitch duration 5) 200 ns 0.01 µF VDD 0.01 µF EXTERNAL RESET CIRCUIT 5) USER VDD 4.7k Ω Required if LVD is disabled Recommended if LVD is disabled ST72XXX PULSE GENERATOR Filter RON VDD WATCHDOG LVD RESET INTERNAL RESET |
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