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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72325 датащи(PDF) 120 Page - STMicroelectronics |
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ST72325 датащи(HTML) 120 Page - STMicroelectronics |
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120 / 196 page  120/196 I2C BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call ad- dress can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast I2C (up to 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (Fscl) is controlled by a pro- grammable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 68. I2C Interface Block Diagram DATA REGISTER (DR) DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 (OAR1) CLOCK CONTROL REGISTER (CCR) STATUS REGISTER 1 (SR1) CONTROL REGISTER (CR) CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT CLOCK CONTROL DATA CONTROL SCL or SCLI SDA or SDAI OWN ADDRESS REGISTER 2 (OAR2) |
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