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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F269 датащи(PDF) 136 Page - STMicroelectronics |
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ST10F269 датащи(HTML) 136 Page - STMicroelectronics |
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136 / 160 page  ST10F269 136/160 21.4 - AC characteristics 21.4.1 - Test Waveforms 21.4.2 - Definition of Internal Timing The internal operation of the ST10F269 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F269. The example for PLL operation shown in Figure 67 refers to a PLL factor of 4. Figure 65 : Input / Output Waveforms Figure 66 : Float Waveforms 2.4V 0.45V Test Points 0.2VDD+0.9 0.2VDD+0.9 0.2VDD-0.1 0.2VDD-0.1 AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Timing Reference Points VLoad +0.1V VLoad -0.1V VOH -0.1V VOL +0.1V VLoad VOL VOH For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA). |
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