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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7FOXF1 датащи(PDF) 127 Page - STMicroelectronics |
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ST7FOXF1 датащи(HTML) 127 Page - STMicroelectronics |
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127 / 226 page  ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals 127/226 Figure 64. Output compare timing diagram, fTIMER =fCPU/4 One pulse mode One pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the input capture1 function and the output compare1 function. Procedure 1. Load the OC1R register with the value corresponding to the length of the pulse (see Equation 3 below). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the output compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see : Timer A Control register 2 (TACR2) on page 134). Internal CPU clock Timer clock Counter register Output compare register i (OCRi) 2ED3 2ED0 2ED1 2ED2 2ED3 2ED4 2ECF OCMPi pin (OLVLi = 1) Output compare flag i (OCFi) |
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