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IS25LE512MG-RMLA2:PTY датащи(PDF) 177 Page - Integrated Silicon Solution, Inc |
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IS25LE512MG-RMLA2:PTY датащи(HTML) 177 Page - Integrated Silicon Solution, Inc |
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177 / 194 page ![]() IS25LE512MG IS25WE512MG Integrated Silicon Solution, Inc.- www.issi.com 177 Rev. A6 10/02/2025 8.72 CLEAR ECC REGISTER OPERATION (CLECC, B6h) A Clear ECC Register (CLECC) instruction clears all ECC register bits [47:1] to “0” except for ECCONOFF bit [0]. Once any bits are set to “1”, they remain set to “1” until they are cleared to “0” with a CLECC command. Figure 8.158 Clear ECC Register Sequence In SPI Mode Instruction = B6h CE# SCK SI 0 1 2 3 4 5 6 7 Mode 3 Mode 0 SO High Impedance Figure 8.159 Clear ECC Register Sequence In QPI Mode B6h CE# SCK IO[3:0] 0 1 Mode 3 Mode 0 |
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