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IS25LE512MG-RMLA2:PTY датащи(PDF) 166 Page - Integrated Silicon Solution, Inc

номер детали IS25LE512MG-RMLA2:PTY
подробное описание детали  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  194 Pages
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производитель  ISSI [Integrated Silicon Solution, Inc]
домашняя страница  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE512MG-RMLA2:PTY датащи(HTML) 166 Page - Integrated Silicon Solution, Inc

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IS25LE512MG
IS25WE512MG
Integrated Silicon Solution, Inc.- www.issi.com
166
Rev. A6
10/02/2025
8.64 GANG SECTOR/BLOCK LOCK OPERATION (GBLK, 7Eh)
The Gang Sector/Block Lock (GBLK) instruction provides a quick method to set all DYB (Dynamic Protection Bit)
bits to “0” at once.
Before the GBLK (7Eh) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The sequence of issuing GBLK instruction is: drive CE# low → send GBLK instruction code → drive CE# high.
The instruction code will be shifted into the device on the rising edge of SCK.
The GBLK command is accepted in both SPI and QPI mode. The CE# must go high exactly at the byte boundary,
otherwise, the instruction will be ignored. While the GBLK operation is in progress, the Status Register or Extended
Read Register may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the
GBLK operation, and is “0” when it is completed.
It takes 70us (typ) to complete GBLK operation.
Figure 8.143 Gang Sector/Block Lock Sequence In SPI Mode
Instruction = 7Eh
CE#
SCK
SI
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SO
High Impedance
Figure 8.144 Gang Sector/Block Lock Sequence In QPI Mode
7Eh
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0



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