IS25LE512MG-RLLA2:PTY datasheet(159/194 Pages) ISSI

номер детали	IS25LE512MG-RLLA2:PTY

подробное описание детали	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	194 Pages

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производитель	ISSI [Integrated Silicon Solution, Inc]

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159 / 194 page

IS25LE512MG

IS25WE512MG

Integrated Silicon Solution, Inc.- www.issi.com

159

Rev. A6

10/02/2025

8.57 PROGRAM ASP OPERATION (PGASP, 2Fh)

Before the Program ASP (PGASP) command can be accepted by the device, a Write Enable (WREN) command

must be issued. After the WREN command has been decoded, the device will set the Write Enable Latch (WEL) in

the Status Register to enable any write operations.

The PGASP command is entered by driving CE# low, followed by the instruction code and two data bytes, least

significant byte first, most significant bit of each byte first. The ASP Register is two data bytes in length. The PGASP

command affects the Write In Progress (WIP) bit in the same manner as any other programming operation.

CE# input must be driven high after the sixteenth bit of data has been latched in. If not, the PGASP command is

not executed. As soon as CE# is driven high, the PGASP operation is initiated. While the PGASP operation is in

progress, the Status Register or the Extended Read Register may be read to check the value of WIP bit. The WIP

bit is “1” during the PGASP operation, and is “0” when it is completed. When the PGASP operation is completed,

the WEL is set to “0”.

Figure 8.129 Program ASP Sequence In SPI Mode

Instruction = 2Fh

CE #

SCK

...

Mode 3

Mode 0

1st byte Data In

High Impedence

...

2nd byte Data In

Figure 8.130 Program ASP Sequence In QPI Mode

2Fh

SCK

IO[3:0]

Mode 3

Mode 0

1st byte

Data In

2nd byte

Data In

CE#

IS25LE512MG-RLLA2:PTY датащи(PDF) 159 Page - Integrated Silicon Solution, Inc