SPSB100 datasheet(202/213 Pages) STMICROELECTRONICS

202 / 213 page

3.8.2

USER-NVM emulation ................................................... 37

3.8.3

USER-NVM programming procedure ........................................ 38

3.8.4

Loading USER-NVM data in RAM image ..................................... 38

3.9

Wake-up inputs: IGN and WU ................................................... 38

3.10

Configurable time-out window watchdog .......................................... 39

3.11

FIN1 input.................................................................... 40

3.11.1

Static protocol .......................................................... 40

3.11.2

Dynamic protocol ....................................................... 40

3.11.3

Reaction on error ....................................................... 41

3.12

High-side output OUT_HS ...................................................... 41

3.13

Fail-safe output - NFSO1 ....................................................... 41

3.14

Interrupt - IRQ ................................................................ 43

3.15

Reset output - NRST .......................................................... 47

3.16

10-bit ADC ................................................................... 47

3.17

SW-Debug mode.............................................................. 47

3.18

VREG ....................................................................... 48

Protection, diagnosis and monitoring signals .....................................49

4.1

Supply monitoring ............................................................. 49

4.1.1

VS pin ................................................................ 49

4.1.2

FBB pin ............................................................... 49

4.1.3

VIO pin ............................................................... 49

4.2

Regulators output voltage protection ............................................. 49

4.3

Boost and bypass Vds monitoring ................................................ 49

4.4

Boost activity monitoring ....................................................... 50

4.5

WU and IGN monitoring ........................................................ 50

4.6

Ground pin monitoring ......................................................... 50

4.7

Temperature monitoring ........................................................ 50

4.8

HW low-level monitors ......................................................... 52

4.9

Communication interface ....................................................... 52

4.10

IRQ pin monitoring ............................................................ 53

4.11

NRST pin monitoring .......................................................... 53

4.12

NFSO1 pin monitoring ......................................................... 53

4.13

Watchdog block monitoring ..................................................... 53

4.14

FCCU block monitoring ........................................................ 54

4.15

Analog BIST.................................................................. 54

4.16

Logic BIST ................................................................... 54

SPSB100

Contents

DS14640 - Rev 2

page 202/213

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