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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPSB100 датащи(PDF) 135 Page - STMicroelectronics |
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SPSB100 датащи(HTML) 135 Page - STMicroelectronics |
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135 / 213 page  9.6 U_NVM registers During the emulation mode (described in the Section 3.8.2: USER-NVM emulation) U_NVM SPI registers from DCR10 to DRC28 can be R/W, instead after valid USER-NVM programming procedure the U_NVM SPI registers from DCR10 to DRC28 can be only readable as showed below. Table 107. DCR10 (0x0A) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) - (R0) - (R0) - (R0) - (R) - (R) - (R) - (R) RES RES RES RES BUCK1_FREQ BUCK1_PU_VALUE_1 BUCK1_PU_VALUE_0 BUCK1_PU_STEP_ENA_2 Reserved Reserved Reserved Reserved BUCK1 frequency bit BUCK1 pull-up value bit 1 BUCK1 pull-up value bit 0 BUCK1 pull-up step enables bit 2 Table 108. DCR10 (0x0A) MSB description Bit Name Description 23 RES Reserved 22 RES Reserved 21 RES Reserved 20 RES Reserved 19 BUCK1_FREQ BUCK1 frequency: 1: 0.4 MHz 0: 2.4 MHz 18 BUCK1_PU_VALUE_1 BUCK1 voltage setting 00: 3.3 V 01: 5.0 V 1X: 6.5 V 17 BUCK1_PU_VALUE_0 16 BUCK1_PU_STEP_ENA_2 Table 109. DCR10 (0x0A) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 - (R) - (R) - (R) - (R) - (R) - (R) - (R) - (R) BUCK1_PU_STEP_ENA_1 BUCK1_PU_STEP_ENA_0 BUCK1_PD_STEP_OFF_2 BUCK1_PD_STEP_OFF_1 BUCK1_PD_STEP_OFF_0 BUCK1_IPEAK_2 BUCK1_IPEAK_1 BUCK1_IPEAK_0 BUCK1 pull-up step enables bit 1 BUCK1 pull-up step enables bit 0 BUCK1 power-down step off bit 2 BUCK1 power-down step off bit 1 BUCK1 power-down step off bit 0 BUCK1 peak limitation current bit 2 BUCK1 peak limitation current bit 1 BUCK1 peak limitation current bit 0 Table 110. DCR10 (0x0A) description Bit Name Description 15 BUCK1_PU_STEP_ENA_1 14 BUCK1_PU_STEP_ENA_0 To define BUCK1 turn-on steps 000: BUCK is not turned ON 001: Step 1 010: Step 2 011: Step 3 100: Step 4 101: Step 5 110: Step 6 111: Step 7 SPSB100 SPI registers DS14640 - Rev 2 page 135/213 |
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