L9908 datasheet(150/152 Pages) STMICROELECTRONICS

150 / 152 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Pin connection diagram (top view)....................................................... 4

Figure 3.

Pin voltage ranges ................................................................. 7

Figure 4.

14 V pulse scenario - applicative condition ................................................. 9

Figure 5.

2s2p PCB with thermal vias .......................................................... 14

Figure 6.

Safe states activation paths .......................................................... 19

Figure 7.

Damage protected activation simplified structure............................................ 20

Figure 8.

Internal supply operative range ........................................................ 22

Figure 9.

VDD functional ranges.............................................................. 23

Figure 10.

Internal reset logic simplified block diagram ............................................... 25

Figure 11.

Device operational state machine ...................................................... 26

Figure 12.

CONFIG mode state machine......................................................... 29

Figure 13.

Self-test mode state machine (NORMAL MODE) ........................................... 31

Figure 14.

Fault output redirection logic simplified block diagram ........................................ 35

Figure 15.

Shutdown fault - Transient fault timing diagram ............................................. 36

Figure 16.

Shutdown fault - Permanent fault timing diagram............................................ 36

Figure 17.

Auto-retry faults - Transient fault timing diagram ............................................ 37

Figure 18.

Auto-retry faults - Permanent fault timing diagram ........................................... 38

Figure 19.

Reduced operation fault - Transient fault timing diagram ...................................... 39

Figure 20.

Reduced operation fault - Permanent fault timing diagram ..................................... 39

Figure 21.

Warning - Transient fault timing diagram ................................................. 40

Figure 22.

Warning - Permanent fault timing diagram ................................................ 40

Figure 23.

Power-Up diagram ................................................................ 42

Figure 24.

Recommended Power-Up sequence .................................................... 43

Figure 25.

VDH operative range ............................................................... 47

Figure 26.

Ext. FET gate supply simplified block diagram ............................................. 48

Figure 27.

VBP functional ranges .............................................................. 52

Figure 28.

VPRE monitor boot masking.......................................................... 53

Figure 29.

VPRE operative ranges ............................................................. 54

Figure 30.

BT1 behavior timing diagram ......................................................... 56

Figure 31.

VCP UV boot masking .............................................................. 57

Figure 32.

VCP operative range ............................................................... 58

Figure 33.

Pre-drivers Disable mode behavior ..................................................... 59

Figure 34.

Pre-drivers HIZ mode behavior ........................................................ 60

Figure 35.

Pre-drivers delay characteristics ....................................................... 62

Figure 36.

Pre-drivers rise/fall time characteristics .................................................. 62

Figure 37.

Ext. FET Turn-on/off simplified behavior.................................................. 64

Figure 38.

Pre-driver peak output current limitation circuit ............................................. 65

Figure 39.

VGS monitor operative ranges ........................................................ 66

Figure 40.

Dead Time Protection functional operation ................................................ 67

Figure 41.

Interlocking protection on PWM inputs: functional operation .................................... 68

Figure 42.

Shoot-Through diagnosis on PWM inputs: functional operation .................................. 68

Figure 43.

Shoot-through protection on Ext. FET Vgs functional operation .................................. 69

Figure 44.

n-th Current Monitor Channel simplified block diagram........................................ 70

Figure 45.

External Shunts Configurations a) DC-Link, b) 2xSingle Leg + DC-Link, c) 3xSingle Leg ................ 70

Figure 46.

A/D Conversion simplified block diagram ................................................. 72

Figure 47.

Current Monitor input dynamic timings ................................................... 74

Figure 48.

Current monitor input CMRR - Positive Common Mode input voltage .............................. 75

Figure 49.

Current monitor input CMRR - Negative Common Mode input voltage ............................. 75

Figure 50.

Command edge triggering timing diagram ................................................ 77

Figure 51.

Auto-triggering timing diagram ........................................................ 78

Figure 52.

Digital signal processing simplified block diagram ........................................... 78

Figure 53.

Digital LP filtering simplified block diagram ................................................ 79

L9908

List of figures

DS13546 - Rev 5

page 150/152

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