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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA381BWS датащи(PDF) 151 Page - STMicroelectronics |
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STA381BWS датащи(HTML) 151 Page - STMicroelectronics |
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151 / 174 page  DocID018937 Rev 7 151/174 STA381BWS Register description: Sound Terminal compatibility The output PLL frequency formula is: where Fin is the input clock frequency from the pad. Table 164. PLL factors PLL parameter Min Max FRAC 0 65535 IDIV 0 3 NDIV 5 55 Table 165. PLL register 0x43 bits Bit R/W RST Name Description 7 R/W 0 PLL_DITH(1:0) 00: PLL clock dithering disabled 01: PLL clock dithering enabled (triangular)) 10: PLL clock dithering enabled (rectangular) 11: Reserved 6 R/W 0 5 R/W 0 NDIV PLL loop divider 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Table 166. PLL register 0x44 bits Bit R/W RST Name Description 7 R/W 0 PLL_DPD 0: any PLL dividers change is implemented via PLL power-down 1: PLL divider change will happen without PLL power-down 6 R/W 0 PLL_FCT 0: PLL use integer ratio 1: PLL use fractional ratio 5 R/W 0 PLL_STB PLL synchronous divider changes strobe 4 R/W 0 PLL_STBBYP 0: PLL_STB is active 1: PLL_STB control is bypassed 3 R/W 0 PLL_IDIV (3:0) Input PLL divider 2 R/W 0 1 R/W 0 0 R/W 0 Fin NDIV IDIV 1 + --------------------------- FRAC 65536 ----------------- + Obsolete Product(s) - Obsolete Product(s) |
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