STA381BWS datasheet(132/174 Pages) STMICROELECTRONICS

132 / 174 page

STA381BWS

132/174

DocID018937 Rev 7

7.11

Dynamic control registers (addr 0x12 - 0x15)

7.11.1

Limiter 1 attack/release rate

7.11.2

Limiter 1 attack/release threshold

7.11.3

Limiter 2 attack/release rate

7.11.4

Limiter 2 attack/release threshold

The STA381BWS includes two independent limiter blocks (not to be mistaken with the

STCompressorTM, for further details about this feature please refer to Section 4.2). The

purpose of the limiters is to automatically reduce the dynamic range of a recording to

prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic

range for a better listening environment such as a nighttime listening mode which is often

needed for DVDs. The two modes are selected via the DRC bit in Configuration register E

(addr 0x04) on page 116. Each channel can be mapped to either limiter or not mapped,

meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the

present value of each channel that is mapped to it, selects the maximum absolute value of

all these channels, performs the limiting algorithm on that value, and then, if needed, adjusts

the gain of the mapped channels in unison.

The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] bits are

set to 0, else the thresholds are determined by EATHx[6:0]. It is recommended in

anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output

power of an FFX amplifier. Since gain can be added digitally within the STA381BWS, it is

possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when

active, automatically starts reducing the gain. The rate at which the gain is reduced when

the attack threshold is exceeded is dependent upon the attack rate register setting for that

limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1

selects the anticlipping mode.

The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] bits are

set to 0, else the thresholds are determined by ERTHx[6:0]. Settings the ERTHx[7] bits to 1

L1A3

L1A2

L1A1

L1A0

L1R3

L1R2

L1R1

L1R0

01101010

L1AT3

L1AT2

L1AT1

L1AT0

L1RT3

L1RT2

L1RT1

L1RT0

01101001

L2A3

L2A2

L2A1

L2A0

L2R3

L2R2

L2R1

L2R0

01101010

L2AT3

L2AT2

L2AT1

L2AT0

L2RT3

L2RT2

L2RT1

L2RT0

01101001

Obsolete

Product(s)

- Obsolete

Product(s)

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