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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA381BWS датащи(PDF) 121 Page - STMicroelectronics |
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STA381BWS датащи(HTML) 121 Page - STMicroelectronics |
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121 / 174 page  DocID018937 Rev 7 121/174 STA381BWS Register description: Sound Terminal compatibility For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage: 2.0 channels, two full-bridges (OCFG = 00) FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B FFX1A/1B configured as C1B0 (default: ternary) FFX2A/2B configured as C2B0 (default: ternary) FFX3A/3B configured as C3B0 (default: ternary) line out FFX4A/4B configured as C4B0 (default: ternary) line out On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 38. Figure 38. 2.0 channels (OCFG = 00) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B Obsolete Product(s) - Obsolete Product(s) |
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