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STM32F446RC датащи(PDF) 172 Page - STMicroelectronics

номер детали STM32F446RC
подробное описание детали  ARM® Cortex®-M4 32b MCUFPU, 225DMIPS, up to 512kB Flash/1284KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces
PDF  202 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F446RC датащи(HTML) 172 Page - STMicroelectronics

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Electrical characteristics
STM32F446xC/E
172/202
DocID027107 Rev 6
6.3.27
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 104 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 16, with the following configuration:
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
Table 103. LPSDR SDRAM write timings(1)(2)
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
Symbol
Parameter
Min
Max
Unit
F(SDCLK)
Frequency of operation
-
84
MHz
tw(SDCLK)
FMC_SDCLK period
2THCLK - 0.5
2THCLK + 0.5
ns
td(SDCLKL _Data)
Data output valid time
-
5
th(SDCLKL _Data)
Data output hold time
0.5
-
td(SDCLK _Add)
Address valid time
-
3
td(SDCLKL _SDNWE)) SDNWE valid time
-
3
th(SDCLKL_SDNWE)) SDNWE hold time
0
-
td(SDCLKL_SDNE))
Chip select valid time
-
2.5
th(SDCLKL_ SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
-
2
th(SDCLKL_SDNRAS) SDNRAS hold time
0
-
td(SDCLKL_SDNCAS) SDNCAS valid time
-
2
td(SDCLKL_SDNCAS) SDNCAS hold time
0
-
Table 104. DCMI characteristics
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
-0.4
-
DCMI_PIXCLK Pixel clock input
-
54
MHz
DPixel
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
1
-
ns
th(DATA)
Data input hold time
3.5
-
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time
2
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time
0
-



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