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STM32F446RC датащи(PDF) 130 Page - STMicroelectronics

номер детали STM32F446RC
подробное описание детали  ARM® Cortex®-M4 32b MCUFPU, 225DMIPS, up to 512kB Flash/1284KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces
PDF  202 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F446RC датащи(HTML) 130 Page - STMicroelectronics

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Electrical characteristics
STM32F446xC/E
130/202
DocID027107 Rev 6
Figure 36. SPI timing diagram - slave mode and CPHA = 0
tw(SCKH)
SCK high and low time
Master mode, SPI presc = 2
TPCLK - 1.5
TPCLK TPCLK + 1.5
ns
tw(SCKL)
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4TPCLK
--
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2TPCLK
tsu(MI)
Data input setup time
Master mode
4
-
-
tsu(SI)
Slave mode
3
-
-
th(MI)
Data input hold time
Master mode
4
-
-
th(SI)
Slave mode
2
-
-
ta(SO)
Data output access time Slave mode
7
-
21
tdis(SO)
Data output disable time Slave mode
5
-
12
tv(SO)
Data output valid/hold
time
Slave mode (after enable edge),
2.7V ≤ VDD ≤ 3.6V
-7.5
22
Slave mode (after enable edge),
1.7 V ≤ VDD ≤ 3.6 V
-
7.5
10.5
th(SO)
Data output valid/hold
time
Slave mode (after enable edge)
5
-
-
tv(MO)
Data output valid time
Master mode (after enable edge)
-
1.5
5
th(MO)
Data output hold time
Master mode (after enable edge)
0
-
-
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
Table 63. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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