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ST10F271Z1 датащи(PDF) 175 Page - STMicroelectronics

номер детали ST10F271Z1
подробное описание детали  16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
PDF  185 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST10F271Z1 датащи(HTML) 175 Page - STMicroelectronics

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Electrical characteristics
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Figure 61.
CLKOUT and READY
1.
Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2.
The leading edge of the respective command depends on RW-delay.
3.
READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5.
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is
guaranteed, if READY is removed in response to the command (see Note 4).
6.
Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
7.
The next external bus cycle may start here.
t30
t34
t35
t36
t35
t36
t58
t59
t58
t59
wait state
READY
MUX / Tri-state 6)
t32
t33
t29
Running cycle 1)
t31
t37
3)
3)
5)
t60 4)
6)
2)
7)
3)
3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY



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