STM32MP151AAA3T datasheet(196/245 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32MP151A

196/245

DS12500 Rev 1

General PCB design guidelines

PCB design guidelines are provided in AN5031 “Getting started with STM32MP1 Series

hardware development.” available from the ST website www.st.com.

6.3.22

DAC electrical characteristics

Table 75. DAC characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply voltage

1.8

3.3

3.6

VREF+

Positive reference voltage

1.80

VDDA

VREF-

Negative reference

voltage

VSSA

Resistive Load

DAC output

buffer ON, Not

valid in Sample

& Hold mode

connected to

VSSA

kΩ

connected to

VDDA

Output Impedance

DAC output buffer OFF

10.3

RBON

Output impedance sample

and hold mode, output

buffer ON

DAC output

buffer ON

VDD = 2.7 V

1.6

kΩ

VDD = 2.0 V

2.6

RBOFF

Output impedance sample

and hold mode, output

buffer OFF

DAC output

buffer OFF

VDD = 2.7 V

17.8

kΩ

VDD = 2.0 V

18.7

Capacitive Load

DAC output buffer OFF

CSH

Sample and Hold mode

0.1

µF

VDAC_OUT

Voltage on DAC_OUT

output

DAC output buffer ON

0.2

VDDA

-0.2(2)

DAC output buffer OFF

VREF+

tSETTLING

Settling time (full scale: for

a 12-bit code transition

between the lowest and

the highest input codes

when DAC_OUT reaches

the final value of ±0.5LSB,

±1LSB, ±2LSB, ±4LSB,

±8LSB)

Normal mode,

DAC output

buffer ON,

CL ≤ 10 pF

RL ≥ 5 kΩ

±0.5 LSB

TBD

µs

±1 LSB

±2 LSB

TBD

±4 LSB

TBD

±8 LSB

TBD

Normal mode,

DAC output buffer OFF,

+/-1LSB, Cload ≤ 10 pF

-2-

tWAKEUP(3)

Wakeup time from off

state (setting the Enx bit in

the DAC Control register)

until the ±1LSB final value

Normal mode,

DAC output buffer ON,

CL ≤ 50 pF, RL ≥ 5 kΩ

-5-

µs

Normal mode,

DAC output buffer OFF,

CL ≤ 10 pF

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