PIC12LF1501 datasheet(168/352 Pages) MICROCHIP

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PIC16(L)F1503

DS40001607D-page 168

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21.4

I2C

MODE OPERATION

All MSSP I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC®

microcontroller and user software. Two pins, SDAx

and SCLx, are exercised by the module to communi-

cate with other external I2C devices.

21.4.1

BYTE FORMAT

All communication in I2C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa,

followed by an Acknowledge bit sent back. After the

eighth falling edge of the SCLx line, the device output-

ting data on the SDAx changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

The clock signal, SCLx, is provided by the master.

Data is valid to change while the SCLx signal is low,

and sampled on the rising edge of the clock. Changes

on the SDAx line while the SCLx line is high define

special conditions on the bus, explained below.

21.4.2

DEFINITION OF I2C TERMINOLOGY

There is language and terminology in the description

of I2C communication that have definitions specific to

I2C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I2CTM

specification.

21.4.3

SDAX AND SCLX PINS

Selection of any I2C mode with the SSPEN bit set,

forces the SCLx and SDAx pins to be open-drain.

These pins should be set by the user to inputs by set-

ting the appropriate TRIS bits.

21.4.4

SDAX HOLD TIME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the

time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns mini-

mum hold time and may help on buses with large

capacitance.

TABLE 21-2:

I2C BUS TERMS

Note:

Data is tied to output zero when an I2C

mode is enabled.

TERM

Description

Transmitter

The device which shifts data out

onto the bus.

Receiver

The device which shifts data in

from the bus.

Master

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave

The device addressed by the

master.

Multi-master

A bus with more than one device

that can initiate data transfers.

Arbitration

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDAx and SCLx lines are

high.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPxADD.

Write Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCLx low to stall communication.

Bus Collision

Any time the SDAx line is sampled

low by the module while it is out-

putting and expected high state.

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