LAN9252VSLASHML datasheet(135/329 Pages) MICROCHIP

135 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 135

LAN9252

CRC[10] = CRC[2]

CRC[9] = CRC[1] ^ F0

CRC[8] = CRC[0] ^ F1

CRC[7] = F0 ^ F2

CRC[6] = F1 ^ F3

CRC[5] = F2 ^ F4

CRC[4] = F3 ^ F5

CRC[3] = F4 ^ F6

CRC[2] = F5 ^ F7

CRC[1] = F6

CRC[0] = F7

Determine the offset pattern with offset 0 being the first byte of the destination address. Update the offset in the

Filter Pattern Offset field of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x).

Determine Address Matching Conditions:

Determine the address matching scheme based on Table 11-4 and update the Filter Broadcast Enable, Filter Any

Multicast Enable, and Address Match Enable bits of the PHY x Wakeup Filter Configuration Register A

(PHY_WUF_CFGA_x) accordingly.

If necessary (see step 4), set the desired MAC address to cause the wake event in the PHY x MAC Receive

Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and

PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x).

Set the Filter Enable bit of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) to enable

the filter.

Enable Wakeup Frame Detection:

Set the Wakeup Frame Enable (WUEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x)

to enable Wakeup Frame detection.

Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable

WoL events.

When a match is triggered, the Remote Wakeup Frame Received (WUFR) bit of the PHY x Wakeup Control and Status

Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) will be set.

11.2.10

RESETS

In addition to the chip-level hardware reset (RST#), EtherCAT system reset, and Power-On Reset (POR), the PHY sup-

ports three block specific resets. These are discussed in the following sections. For detailed information on all device

resets and the reset sequence refer to Section 6.2, "Resets," on page 38.

11.2.10.1

PHY Software Reset via RESET_CTL

The PHYs can be reset via the Reset Control Register (RESET_CTL). These bits are self clearing after approximately

102 us. This reset does not reload the configuration strap values into the PHY registers.

11.2.10.2

PHY Software Reset via PHY_BASIC_CTRL_x

The PHY can also be reset by setting the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BA-

SIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the

configuration strap values into the PHY registers.

Note:

Only a hardware reset (RST#), Power-On Reset (POR) or EtherCAT system reset will automatically reload

the configuration strap values into the PHY registers.

The Digital Reset (DIGITAL_RST) bit in the Reset Control Register (RESET_CTL) does not reset the

PHYs.

For all other PHY resets, PHY registers will need to be manually configured via software.

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