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LAN9252V/ML датащи(PDF) 119 Page - Microchip Technology

номер детали LAN9252V/ML
подробное описание детали  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252V/ML датащи(HTML) 119 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 119
LAN9252
10.3
SPI/SQI Timing Requirements
Note 3:
The Read instruction is limited to 30 MHz maximum
Note 4:
Depends on loading of 30 pF or 10 pF
Note 5:
Depending on the clock frequency and pulse width, data may not be valid until following the next rising edge
of SCK. The host SPI controller may need to delay the sampling of the data by either a fixed time or by using
the falling edge of SCK.
FIGURE 10-17:
SPI/SQI INPUT TIMING
FIGURE 10-18:
SPI/SQI OUTPUT TIMING
TABLE 10-3:
SPI/SQI TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
fsck
SCK clock frequency Note 3
30 / 80
MHz
thigh
SCK high time
5.5
ns
tlow
SCK low time
5.5
ns
tscss
SCS# setup time to SCK
5ns
tscsh
SCS# hold time from SCK
5ns
tscshl
SCS# inactive time
50
ns
tsu
Data input setup time to SCK
3ns
thd
Data input hold time from SCK
4ns
ton
Data output turn on time from SCK
0ns
tv
Data output valid time from SCK Note 4, Note 5
11.0/9.0
ns
tho
Data output hold time from SCK
0ns
tdis
Data output disable time from SCS# inactive
20
ns
SCK
SI/SIO[3:0]
SCS#
tscss
thigh
tlow
tsu
thd
tscshl
tscsh
SO/SIO[3:0]
SCK
thigh
tlow
SCS#
tdis
ton
tv
tho



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