LAN9252VSLASHML datasheet(102/329 Pages) MICROCHIP

102 / 329 page

LAN9252

DS00001909A-page 102

 2015 Microchip Technology Inc.

10.0

SPI/SQI SLAVE

10.1

Functional Overview

The SPI/SQI Slave module provides a low pin count synchronous slave interface that facilitates communication between

the device and a host system. The SPI/SQI Slave allows access to the System CSRs and internal FIFOs and memories.

It supports single and multiple register read and write commands with incrementing, decrementing and static address-

ing. Single, Dual and Quad bit lanes are supported in SPI mode with a clock rate of up to 80 MHz. SQI mode always

uses four bit lanes and also operates at up to 80 MHz.

The following is an overview of the functions provided by the SPI/SQI Slave:

• Serial Read: 4-wire (clock, select, data in and data out) reads at up to 30 MHz. Serial command, address and

data. Single and multiple register reads with incrementing, decrementing or static addressing.

• Fast Read: 4-wire (clock, select, data in and data out) reads at up to 80 MHz. Serial command, address and data.

Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static

addressing.

• Dual / Quad Output Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command and

address, parallel data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decre-

menting or static addressing.

• Dual / Quad I/O Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command, parallel

address and data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decre-

menting or static addressing.

• SQI Read: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data.

Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static

addressing.

• Write: 4-wire (clock, select, data in and data out) writes at up to 80 MHz. Serial command, address and data. Sin-

gle and multiple register writes with incrementing, decrementing or static addressing.

• Dual / Quad Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial command and

address, parallel data. Single and multiple register writes with incrementing, decrementing or static addressing.

• Dual / Quad Address / Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial com-

mand, parallel address and data. Single and multiple register writes with incrementing, decrementing or static

addressing.

• SQI Write: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data. Single

and multiple register writes with incrementing, decrementing or static addressing.

10.2

SPI/SQI Slave Operation

Input data on the SIO[3:0] pins is sampled on the rising edge of the SCK input clock. Output data is sourced on the

SIO[3:0] pins with the falling edge of the clock. The SCK input clock can be either an active high pulse or an active low

pulse. When the SCS# chip select input is high, the SIO[3:0] inputs are ignored and the SIO[3:0] outputs are three-

stated.

In SPI mode, the 8-bit instruction is started on the first rising edge of the input clock after SCS# goes active. The instruc-

tion is always input serially on SI/SIO0.

For read and write instructions, two address bytes follow the instruction byte. Depending on the instruction, the address

bytes are input either serially, or 2 or 4 bits per clock. Although all registers are accessed as DWORDs, the address field

is considered a byte address. Fourteen address bits specify the address. Bits 15 and 14 of the address field specifies

that the address is auto-decremented (10b) or auto-incremented (01b) for continuous accesses.

For some read instructions, dummy byte cycles follow the address bytes. The device does not drive the outputs during

the dummy byte cycles. The dummy byte(s) are input either serially, or 2 or 4 bits per clock.

For read and write instructions, one or more 32-bit data fields follow the dummy bytes (if present, else they follow the

address bytes). The data is input either serially, or 2 or 4 bits per clock.

SQI mode is entered from SPI with the Enable Quad I/O (EQIO) instruction. Once in SQI mode, all further command,

addresses, dummy bytes and data bytes are 4 bits per clock. SQI mode can be exited using the Reset Quad I/O

(RSTQIO) instruction.

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