LAN9252VSLASHML datasheet(196/329 Pages) MICROCHIP

196 / 329 page

LAN9252

DS00001909A-page 196

 2015 Microchip Technology Inc.

12.0

ETHERCAT

12.1

EtherCAT Functional Overview

The EtherCAT module implements a 3 port EtherCAT slave controller with 4K bytes of Dual Port memory (DPRAM), 4

SyncManagers, 3 Fieldbus Memory Management Units (FMMUs) and a 64-bit Distributed Clock.

Each port receives an Ethernet frame, performs frame checking and forwards it to the next port. Time stamps of received

frames are generated when they are received. The Loop-back function of each port forwards Ethernet frames to the

next logical port if there is either no link at a port, or if the port is not available, or if the loop is closed for that port. The

Loop-back function of port 0 forwards the frames to the EtherCAT Processing Unit. The loop settings can be controlled

by the EtherCAT master.

Packets are forwarded in the following order: Port 0->EtherCAT Processing Unit->Port 1->Port 2.

The EtherCAT Processing Unit (EPU) receives, analyses and processes the EtherCAT data stream. The main purpose

of the EtherCAT Processing unit is to enable and coordinate access to the internal registers and the memory space of

the ESC, which can be addressed both from the EtherCAT master and from the local application. Data exchange

between master and slave application is comparable to a dual-ported memory (process memory), enhanced by special

functions e.g. for consistency checking (SyncManager) and data mapping (FMMU).

Each FMMU performs the task of bitwise mapping of logical EtherCAT system addresses to physical addresses of the

device.

SyncManagers are responsible for consistent data exchange and mailbox communication between EtherCAT master

and slaves. Each SyncManager's direction and mode of operation is configured by the EtherCAT master. Two modes

of operation are available: buffered mode or mailbox mode. In the buffered mode, both the local microcontroller and

EtherCAT master can write to the device concurrently. The buffer within the LAN9252 will always contain the latest data.

If newer data arrives before the old data can be read out, the old data will be dropped. In mailbox mode, access to the

buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guaranteeing that no data

will be dropped.

Distributed Clocks (DC) allow for precisely synchronized generation of output signals and input sampling, as well as

time stamp generation of events.

The EtherCAT chapter consists of the following main sections:

• Section 12.2, "Distributed Clocks," on page 197

• Section 12.3, "PDI Selection and Configuration," on page 198

• Section 12.4, "Digital I/O PDI," on page 198

• Section 12.5, "Host Interface PDI," on page 200

• Section 12.6, "GPIOs," on page 201

• Section 12.7, "User RAM," on page 201

• Section 12.8, "EEPROM Configurable Registers," on page 201

• Section 12.9, "Port Interfaces," on page 202

• Section 12.10, "LEDs," on page 208

• Section 12.11, "EtherCAT CSR and Process Data RAM Access," on page 208

• Section 12.12, "EtherCAT Reset," on page 213

• Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214

• Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223

Refer to FIGURE 2-2: Internal Block Diagram on page 9 for an overview of the interconnection of the EtherCAT module

within the device.

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