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LAN9252/ML датащи(PDF) 262 Page - Microchip Technology |
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LAN9252/ML датащи(HTML) 262 Page - Microchip Technology |
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262 / 329 page ![]() LAN9252 DS00001909A-page 262 2015 Microchip Technology Inc. Note 20: Error bits are cleared by writing “000” (or any valid command) to Command Register bits. Note 21: Write access is possible if EEPROM interface is busy (Busy bit = 1). PDI acknowledges pending commands by writing a 1 into the corresponding command register bits 10:8. Errors can be indicated by writing a 1 into the error bits (11 and 13). Acknowledging clears bit 5 of the AL Event Request Register. Note 22: The Command Register bits are self clearing after the command is executed (EEPROM Busy ends). Writing “000” to the Command Register bits will also clear the error bits 14:13. The Command Register bits are ignored if the Error Acknowledge/Command is pending. Note 23: The default of this bit is dependent on the eeprom_size_strap. Note 24: The ECAT Write Enable bit is self clearing at the SOF of the next frame. Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 10:8 Command Register Write: Initiate command Read: Currently executed command 000: No command/EEPROM idle (clear error bits) 001: Read 010: Write 100: Reload Others: RESERVED / invalid commands (no not issue) (See Note 22) R/W R/[W] Note 21 000b 7 Selected EEPROM Algorithm 0: 1 address byte (1Kbit - 16Kbit EEPROMs) 1: 2 address bytes (32Kbit - 4Mbit EEPROMs) RO RO Note 23 6 Supported Number of EEPROM Bytes 0: 4 Bytes 1: 8 Bytes RO RO 0b 5 EEPROM Emulation 0: Normal operation (I2C interface used) 1: PDI emulates EEPROM (I2C not used) Note: Must be written as 0. RO RO 0b 4:1 RESERVED RO RO 0b 0 ECAT Write Enable 0: Write requests are disabled 1: Write requests are enabled (See Note 24) R/W RO 0b Bits Description ECAT Type PDI Type Default |
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