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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9252/ML датащи(PDF) 221 Page - Microchip Technology |
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LAN9252/ML датащи(HTML) 221 Page - Microchip Technology |
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221 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 221 LAN9252 12.13.7 ETHERCAT PROCESS RAM WRITE ADDRESS AND LENGTH REGISTER (ECAT_PRAM_WR_ADDR_LEN) This read/write register is used in conjunction with the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_- DATA) and the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) to perform write opera- tions to the EtherCAT Core Process RAM. Offset: 310h Size: 32 bits Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Bits Description Type Default 31:16 PRAM Write Length (PRAM_WRITE_LEN) This field indicates the number of bytes to be written to the EtherCAT Core Process RAM. It is decremented as data is written to the EtherCAT Core from the FIFO. The host should not modify this field unless the PRAM Write Busy (PRAM_WRITE_BUSY) bit is a low. R/W 0000h 15:0 PRAM Write Address (PRAM_WRITE_ADDR) This field indicates the EtherCAT Core byte address to be written. It is incre- mented as data is written to the EtherCAT Core from the FIFO. Note: The Process RAM starts at address 1000h. The host should not modify this field unless the PRAM Write Busy (PRAM_WRITE_BUSY) bit is a 0. R/W 0000h |
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