ST10F272E datasheet(151/181 Pages) STMICROELECTRONICS

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ST10F272B/ST10F272E

Electrical characteristics

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The PLL input frequency range is limited to 1 to 3.5MHz, while the VCO oscillation range is

64 to 128MHz. The CPU clock frequency range when PLL is used is 16 to 64MHz.

Example 1

●

FXTAL = 4MHz

●

P0(15:13) = ‘110’ (Multiplication by 3)

●

PLL Input Frequency = 1MHz

●

VCO frequency = 48MHz

●

PLL Output Frequency = 12MHz

(VCO frequency divided by 4)

●

FCPU = 12MHz (no effect of Output Prescaler)

Example 2

●

FXTAL = 8MHz

●

P0(15:13) = ‘100’ (Multiplication by 5)

●

PLL Input Frequency = 2MHz

●

VCO frequency = 80MHz

●

PLL Output Frequency = 40MHz (VCO frequency divided by 2)

●

FCPU = 40MHz (no effect of Output Prescaler)

24.8.9

PLL Jitter

The following terminology is hereafter defined:

●

Self referred single period jitter

Also called “Period Jitter”, it can be defined as the difference of the Tmax and Tmin,

where Tmax is maximum time period of the PLL output clock and Tmin is the minimum

time period of the PLL output clock.

●

Self referred long term jitter

Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where

Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the

minimum time difference between N+1 clock rising edges. Here N should be kept

sufficiently large to have the long term jitter. For N=1, this becomes the single period

jitter.

Jitter at the PLL output can be due to the following reasons:

●

Jitter in the input clock

●

Noise in the PLL loop.

4 to 6.4MHz

FXTAL / 2

–

FXTAL x 10

4 to 12MHz 1)

–

PLL bypassed

FPLL / 2

FXTAL / 2

4MHz

FXTAL / 2

–

FXTAL x 16

Table 69.

Internal PLL divider mechanism (continued)

P0.15-13

(P0H.7-5)

XTAL

Frequency

Input

Prescaler

PLL

Output

Prescaler

CPU Frequency

fCPU = fXTAL x F

Multiply by

Divide by

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