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ST10F272E датащи(PDF) 110 Page - STMicroelectronics |
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ST10F272E датащи(HTML) 110 Page - STMicroelectronics |
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110 / 181 page ![]() Power reduction modes ST10F272B/ST10F272E 110/181 Warning: During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. 21.3.2 Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V18SB internal reference (derived from VSTBY pin external voltage). It is recommended to held the device under RESET (RSTIN pin forced low) until external VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V18 becomes higher than about 1.0V, there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch. The external hardware shall be responsible to drive low the RSTIN pin until the VDD is stable, even though the internal LVD is active. Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V18. At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM. 21.3.3 Real time clock and stand-by mode When Stand-by mode is entered (turning off the main supply VDD), the Real Time Clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: Being the main oscillator powered by VDD, once this is switched off, the oscillator is stopped. |
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