ST10F271 datasheet(151/173 Pages) STMICROELECTRONICS

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ST10F271

Electrical characteristics

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Figure 49.

External clock drive XTAL1

Note:

When Direct Drive is selected, an external clock source can be used to drive XTAL1. The

maximum frequency of the external clock source depends on the duty cycle: when 64MHz is

used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when for instance

32MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again

equal to 7.8ns).

24.8.14

Memory cycle variables

The tables below use three variables which are derived from the BUSCONx registers and

represent the special characteristics of the programmed memory cycle. The following table

describes, how these variables are to be computed.

24.8.15

External memory bus timing

The following sections include the External Memory Bus timings. The given values are

computed for a maximum CPU clock of 40MHz.

Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the

timing formulas become zero or negative which, in most cases is not acceptable or not

meaningless at all. In these cases, it is necessary to relax the speed of the bus setting

properly tA, tC and tF.

Note:

All External Memory Bus Timings and SSC Timings reported in the following tables are

granted by Design Characterization and not fully tested in production.

24.8.16

Multiplexed bus

VDD = 5V ± 10%, VSS = 0V, TA = –40 to +125°C, CL = 50pF,

ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40MHz CPU clock without wait states)

VIL2

tOSC

VIH2

Table 76.

Memory cycle variables

Description

Symbol

Values

ALE Extension

TCL x [ALECTL]

Memory Cycle Time wait states

2TCL x (15 - [MCTC])

Memory Tri-state Time

2TCL x (1 - [MTTC])

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