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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F272M датащи(PDF) 166 Page - STMicroelectronics |
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ST10F272M датащи(HTML) 166 Page - STMicroelectronics |
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166 / 175 page  Electrical characteristics ST10F272M 166/176 Figure 60. External bus arbitration (regaining the bus) 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F272M requesting the bus. 2. The next ST10F272M driven bus cycle may start here. 24.8.20 High-speed synchronous serial interface (SSC) timing 24.8.20.1 Master mode VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF CLKOUT HOLD HLDA Other signals t62 CSx (On P6.x) t67 t62 (1) (2) t65 t61 BREQ t63 t62 Table 74. SSC master mode timings Symbol Parameter Maximum baudrate 6.6 Mbaud(1) @fCPU = 40 MHz (<SSCBR> = 0002h) Variable baudrate (<SSCBR> = 0001h - FFFFh) Unit Min Max Min Max t300 CC SSC clock cycle time(2) 150 150 8TCL 262144 TCL ns t301 CC SSC clock high time 63 – t300 / 2 - 12 – ns t302 CC SSC clock low time 63 – t300 / 2 - 12 – ns t303 CC SSC clock rise time – 10 – 10 ns t304 CC SSC clock fall time – 10 – 10 ns t305 CC Write data valid after shift edge – 15 – 15 ns t306 CC Write data hold after shift edge(3) -2–-2 – ns |
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