ST10F272M datasheet(132/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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24.7.1

Conversion timing control

When a conversion is started, first the capacitances of the converter are loaded via the

respective analog input pin to the current analog input voltage. The time to load the

capacitances is referred to as sample time. Next the sampled voltage is converted to a

digital value several successive steps, which correspond to the 10-bit resolution of the ADC.

During these steps the internal capacitances are repeatedly charged and discharged via the

VAREF pin.

The current that has to be drawn from the sources for sampling and changing charges

depends on the time that each respective step takes, because the capacitors must reach

their final voltage level within the given time, at least with a certain approximation. The

maximum current, however, that a source can deliver, depends on its internal resistance.

The time that the two different actions during conversion take (sampling, and converting)

can be programmed within a certain range in the ST10F272M relative to the CPU clock. The

absolute time that is consumed by the different conversion steps therefore is independent

from the general speed of the controller. This allows adjustment of the ST10F272M A/D

converter to the system’s properties:

Analog Switch Resistance(3)(8)

RSW

–

600

1600

Port5

Port1

RAD

–

1300

VAREF can be tied to ground when A/D Converter is not in use: There is increased consumption (approximately 200µA) on

main VDD due to internal analog circuitry not being completely turned off. Therefore, it is suggested to maintain the VAREF

at VDD level even when not in use, and to eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON

VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will

be 0x000H or 0x3FFH, respectively

Not 100% tested, guaranteed by design characterization

During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the

sample time tS, changes of the analog input voltage have no effect on the conversion result.

Values for the sample clock tS depend on programming and can be taken from Table 60: A/D converter programming.

This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register

with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the next

Table 60.

DNL, INL, OFS and TUE are tested at VAREF = 5.0V, VAGND = 0V, VDD = 5.0V. It is guaranteed by design characterization

for all other voltages within the defined voltage range.

‘LSB’ has a value of VAREF/1024.

For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV specification)

occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all

Port5 analog input pins does not exceed 10mA.

For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload

condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog

input pins does not exceed 10mA (either dynamic or static injection), the specified TUE is degraded (± 7LSB). To obtain the

same accuracy, the negative injection current on Port1 pins must not exceed -1mA in case of both dynamic and static

injection.

The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels

with the overload current within the different specified ranges (for both positive and negative injection current).

Refer to scheme shown in Figure 40.

Table 59.

A/D converter characteristics (continued)

Parameter

Symbol

Limit values

Unit

Test condition

Min

Max

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