TMP86FS49AIUG datasheet(131/296 Pages) TOSHIBA

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Page 115

TMP86FS49AIUG

10.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)

This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad-

able to enter the 16-bit PPG mode.

The counter counts up using the internal clock or external clock. When a match between the up-counter and

the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is

switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is

switched to the opposite state again when a match between the up-counter and the timer register (TTREG3,

TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.

Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be

generated. Upon reset, the timer F/F4 is cleared to 0.

(The logic level output from the PPG4 pin is the opposite to the timer F/F4.)

Set the lower byte and upper byte in this order to program the timer register. (TTREG3

→ TTREG4,

PWREG3

→ PWREG4) (Programming only the upper or lower byte should not be attempted.)

For PPG output, set the output latch of the I/O port to 1.

Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since

PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values pro-

grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.

Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not

be obtained.

Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is

stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change

TC4CR<TFF4> upon stopping of the timer.

Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped

CLR (TC4CR).3: Stops the timer

CLR (TC4CR).7: Sets the PPG4 pin to the high level

Note 3: i = 3, 4

Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maxi-

mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or

SLEEP1/2 mode.

Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)

Setting ports

LDW

(PWREG3), 07D0H

: Sets the pulse width.

LDW

(TTREG3), 8002H

: Sets the cycle period.

(TC3CR), 33H

: Sets the operating clock to fc/23, and16-bit PPG mode

(lower byte).

(TC4CR), 057H

: Sets TFF4 to the initial value 0, and 16-bit

PPG mode (upper byte).

(TC4CR), 05FH

: Starts the timer.

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