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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H562VG датащи(PDF) 207 Page - STMicroelectronics |
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STM32H562VG датащи(HTML) 207 Page - STMicroelectronics |
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207 / 270 page  DS14258 Rev 5 207/270 STM32H562xx and STM32H563xx Electrical characteristics 238 Figure 55. ADC conversion timing diagram 3. Slow channels correspond to all ADC inputs except for the fast channels. CLK 1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details). Sampling (1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mux Number of CLK clock cycles = ADC resolution / 2 Total conversion time: 0.5 +Tsamp + N/2 SMP 1/2 Table 97. ADC accuracy(1)(2) Symbol Parameter Conditions Min Typ Max Unit ET Total unadjusted error Fast and slow channels Single ended - ±3.5 ±12 LSB Differential - ±2.5 ±7.5 EO Offset error - Single ended - ±3 ±5.5 - Differential - ±2 ±3.5 EG Gain error - Single ended - ±3.5 ±11 - Differential ±2.5 ±7 ED Differential linearity error - Single ended - ±0.75 +2/-1 - Differential - ±0.75 +2/-1 EL Integral linearity error Fast and slow channels Single ended - ±2 ±6.5 Differential - ±1 ±4 ENOB Effective number of bits Single ended - 10.8 - Bits Differential - 11.5 - SINAD Signal-to-noise and distortion ratio Single ended - 68 - dB Differential - 71 - SNR Signal-to-noise ratio Single ended - 70 - Differential - 72 - THD Total harmonic distortion Single ended - -70 - Differential - -80 - 1. Evaluated by characterization for BGA packages. The values for LQFP package can differ. Not tested in production. 2. ADC DC accuracy values are measured after internal calibration in continuous mode. |
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