ST10F273 datasheet(174/179 Pages) STMICROELECTRONICS

174 / 179 page

Electrical characteristics

ST10F273

174/179

Slave mode

VDD = 5V ±10%, VSS = 0V, TA = -40°C to +125°C, CL = 50pF

Table 82.

SSC slave mode timings

Symbol

Parameter

Max. Baud rate

6.6 MBd (1)

@FCPU = 40 MHz

(<SSCBR> = 0002h)

Maximum Baudrate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to

‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum

baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.

Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after checking that resulting

timings are suitable for the master).

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

Min.

Max.

Min.

Max.

t310

SR SSC clock cycle time (2)

Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.

Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).

150

8TCL

262144 TCL

t311

SR SSC clock high time

–

t310 / 2 – 12

–

t312

SR SSC clock low time

–

t310 / 2 – 12

–

t313

SR SSC clock rise time

–

t314

SR SSC clock fall time

–

t315

Write data valid after shift

edge

–

2TCL + 30

t316

Write data hold after shift

edge

0–

–

t317p

Read data setup time before

latch edge, phase error

detection on (SSCPEN = 1)

–

4TCL + 12

–

t318p

Read data hold time after

latch edge, phase error

detection on (SSCPEN = 1)

–

6TCL + 12

–

t317

Read data setup time before

latch edge, phase error

detection off (SSCPEN = 0)

6–

–

t318

Read data hold time after

latch edge, phase error

detection off (SSCPEN = 0)

–

2TCL + 6

–

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