ST10F273 datasheet(135/179 Pages) STMICROELECTRONICS

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ST10F273

Electrical characteristics

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24.7.1

Conversion timing control

When a conversion is started, first the capacitances of the converter are loaded via the

respective analog input pin to the current analog input voltage. The time to load the

capacitances is referred to as sample time. Next the sampled voltage is converted to a

digital value several successive steps, which correspond to the 10-bit resolution of the ADC.

During these steps the internal capacitances are repeatedly charged and discharged via the

VAREF pin.

The current that has to be drawn from the sources for sampling and changing charges

depends on the time that each respective step takes, because the capacitors must reach

their final voltage level within the given time, at least with a certain approximation. The

maximum current, however, that a source can deliver, depends on its internal resistance.

The time that the two different actions during conversion take (sampling, and converting)

can be programmed within a certain range in the ST10F273 relative to the CPU clock. The

absolute time that is consumed by the different conversion steps therefore is independent

from the general speed of the controller. This allows adjusting the A/D converter of the

ST10F273 to the properties of the system:

Fast Conversion can be achieved by programming the respective times to their absolute

possible minimum. This is preferable for scanning high frequency signals. The internal

resistance of analog source and analog supply must be sufficiently low, however.

High Internal Resistance can be achieved by programming the respective times to a

higher value, or the possible maximum. This is preferable when using analog sources and

supply with a high internal resistance in order to keep the current as low as possible. The

conversion rate in this case may be considerably lower, however.

The conversion times are programmed via the upper four bits of register ADCON. Bit fields

ADCTC and ADSTC are used to define the basic conversion time and in particular the

partition between sample phase and comparison phases. The table below lists the possible

VAREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200µA) on main VDD is

added due to internal analogue circuitry not completely turned off: so, it is suggested to maintain the VAREF at VDD level

even when not in use, and eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register.

VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will

be 0x000H or 0x3FFH, respectively.

Not 100% tested, guaranteed by design characterization.

During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the

sample time tS, changes of the analog input voltage have no effect on the conversion result.

Values for the sample clock tS depends on programming and can be taken from Table 68: A/D converter programming.

This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register

with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from next

Table 68.

DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design characterization

for all other voltages within the defined voltage range.

‘LSB’ has a value of VAREF/1024.

For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV specification)

occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all

Port5 analog input pins does not exceed 10 mA.

For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload

condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog

input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded (± 7LSB). To get the

same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static

injection.

The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels

with the overload current within the different specified ranges (for both positive and negative injection current).

Refer to scheme reported in Figure 38.

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