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TDA4VEN...Q1 датащи(PDF) 190 Page - Texas Instruments

номер детали TDA4VEN...Q1
подробное описание детали  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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производитель  TI [Texas Instruments]
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TDA4VEN...Q1 датащи(HTML) 190 Page - Texas Instruments

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Table 6-100 presents timing conditions for MMC1.
Table 6-100. MMC1/MMC2 Timing Conditions
PARAMETER
MIN
MAX UNIT
Input Conditions
SRI
Input slew rate
Default Speed
High Speed
0.69
2.06
V/ns
UHS–I SDR12
UHS–I SDR25
0.34
1.34
V/ns
UHS–I DDR50
1
2
V/ns
Output Conditions
CL
Output load capacitance
All modes
1
10
pF
PCB Connectivity Requirements
td(Trace Delay)
Propagation delay of each trace
UHS–I DDR50
239
1134
ps
All other modes
126
1386
ps
td(Trace Mismatch
Delay)
Propagation delay mismatch across all
traces
High Speed
UHS–I SDR104
8
ps
UHS–I DDR50
20
ps
All other modes
100
ps
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
www.ti.com
190
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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