ST10F269ZX datasheet(150/184 Pages) STMICROELECTRONICS

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ST10F269

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The real minimum value for TCL depends on the

jitter of the PLL. The PLL tunes fCPU to keep it

locked on fXTAL. The relative deviation of TCL is

the maximum when it is referred to one TCL

period. It decreases according to the formula and

to the Figure 69 given below. For N periods of TCL

the minimum value is computed using the

corresponding deviation DN:

where N = number of consecutive TCL periods

and 1

≤ N ≤ 40. So for a period of 3 TCL periods

(N = 3):

4 - 3/15 = 3.8%

3TCLmin

=3TCLNOM x (1 - 3.8/100)

=3TCLNOM x 0.962

3TCLmin

36.075ns (at fCPU = 40MHz)

3TCLmin

45.1ns (at fCPU = 32MHz)

This is especially important for bus cycles using

wait states and e.g. for the operation of timers,

serial interfaces, etc. For all slower operations and

longer periods (e.g. pulse train generation or

measurement,

lower

Baud

rates,

etc.)

the

deviation caused by the PLL jitter is negligible.

21.4.8 - External Clock Drive XTAL1

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C (PQFP144 devices)

Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input

frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source.

2. The input clock signal must reach the defined levels VIL and VIH2.

TCL

MIN

TCL

NOM

100

-------------

–







4N 15

) %

[]

⁄

–

(

Figure 69 : Approximated Maximum PLL Jitter

Parameter

Symbol

fCPU = fXTAL

fCPU = fXTAL / 2

fCPU = fXTAL x F

F = 1.5/2,/2.5/3/4/5

Unit

min

max

min

max

min

max

Oscillator period

tOSC SR

25 1

–

12.5

–

40 x N

100 x N

High time

10 2

–

5 2

–

10 2

–ns

Low time

10 2

–

5 2

–

10 2

–ns

Rise time

–

3 2

–

3 2

–

3 2

Fall time

–

3 2

–

3 2

–

3 2

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

≤ N ≤ 40 and 10MHz ≤ f

CPU ≤ 40MHz

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