ST10F269ZX datasheet(123/184 Pages) STMICROELECTRONICS

123 / 184 page

ST10F269

19 - POWER REDUCTION MODES

123/184

EXxIN inputs are normally sampled interrupt

inputs. However, the Power Down mode circuitry

uses them as level-sensitive inputs.

An EXxIN (x = 3...0) Interrupt Enable bit (bit

CCxIE in respective CCxIC register) need not be

set to bring the device out of Power Down mode.

An external RC circuit must be connected to RPD

pin, as shown in the Figure 61.

To exit Power Down mode with an external

interrupt, an EXxIN (x = 7...0) pin has to be

asserted for at least 40ns.

This signal enables the internal oscillator and PLL

circuitry, and also turns on the weak pull-down

(see Figure 62).

The discharge of the external capacitor provides a

delay that allows the oscillator and PLL circuits to

stabilize before the internal CPU and Peripheral

clocks are enabled. When the RPD voltage drops

below the threshold voltage (about 2.5V), the

Schmitt trigger clears Q2 flip-flop, thus enabling

the CPU and Peripheral clocks, and the device

resumes code execution.

If the Interrupt was enabled (bit CCxIE=’1’ in the

respective CCxIC register) before entering Power

Down mode, the device executes the interrupt

service routine, and then resumes execution after

the PWRDN instruction (see note below).

If the interrupt was disabled, the device executes

the instruction following PWRDN instruction, and

the Interrupt Request Flag (bit CCxIR in the

respective CCxIC register) remains set until it is

cleared by software.

Note:

Due

the

internal

pipeline,

the

instruction

that

follows

the

PWRDN

instruction is executed before the CPU

performs a call of the interrupt service

routine when exiting power-down mode

0 1:

Interrupt on positive edge (rising)

Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)

1 0:

Interrupt on negative edge (falling)

Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)

1 1:

Interrupt on any edge (rising or falling)

Always enter Power Down mode, exit if EXxIN level changed.

EXIxES(x=7...0)

External Interrupt x Edge Selection Field (x=7...0)

Figure 61 : External R0C0 Circuit on RPD Pin For

Exiting Powerdown Mode with External Interrupt

RPD

VDD

220k

Ω minimum

µF Typical

ST10F269-Q3

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