RELEASED

PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

ii

12

OPERATION ........................................................................................ 182

12.1 MICROPROCESSOR INBAND COMMUNICATION ................. 182

12.2 INTERACTION BETWEEN BUS AND LVDS CONFIGURATIONS

.................................................................................................. 184

12.3 MAXIMUM CELL BIT RATE ...................................................... 193

12.4 MINIMUM PROGRAMMING ..................................................... 194

12.5 JTAG SUPPORT ....................................................................... 196

13

FUNCTIONAL TIMING......................................................................... 203

13.1 SCI-PHY/ANY-PHY INTERFACE .............................................. 203

13.2 CLOCKED SERIAL DATA INTERFACE .................................... 208

14

ABSOLUTE MAXIMUM RATINGS ....................................................... 210

15

D.C. CHARACTERISTICS ....................................................................211

16

MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 215

17

A.C. TIMING CHARACTERISTICS...................................................... 219

18

ORDERING AND THERMAL INFORMATION...................................... 226

19

MECHANICAL INFORMATION............................................................ 227