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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F258-E/SOSQTP датащи(PDF) 165 Page - Microchip Technology |
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PIC18F258-E/SOSQTP датащи(HTML) 165 Page - Microchip Technology |
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165 / 402 page  © 2006 Microchip Technology Inc. DS41159E-page 163 PIC18FXX8 17.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to ‘0’. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12). FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING SDA SCL DX – 1 DX WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPCON1 CKP Master device deasserts clock Master device asserts clock |
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