PIC18F23K20-ESLASHML datasheet(102/420 Pages) MICROCHIP

102 / 420 page

PIC18F2XK20/4XK20

DS41303B-page 100

Advance Information

7.6

Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

Configuration

Words.

External

read

and

write

operations are disabled if code protection is enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

7.7

Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are blocked

during

the

Power-up

Timer

period

(TPWRT,

parameter 33).

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch or software malfunction.

7.8

Using the Data EEPROM

The

data

EEPROM

high-endurance,

byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

total number of write cycles to a single byte (specification

D120). If this is the case, then an array refresh must be

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

TABLE 7-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EEADR

EEADR7

EEADR6

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

EEADRH

—

EEADR9

EEADR8

EEDATA

EEPROM Data Register

EECON2

EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

IPR2

OSCFIP

C1IP

C2IP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

PIR2

OSCFIF

C1IF

C2IF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF

PIE2

OSCFIE

C1IE

C2IE

EEIE

BCLIE

HLVDIE

TMR3IE

CCP2IE

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

Loop

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

0AAh

;

MOVWF

EECON2

; Write 0AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

LOOP

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

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