DSPIC30F2011 datasheet(107/205 Pages) MICROCHIP

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DS70139E-page 105

dsPIC30F2011/2012/3012/3013

15.5.2

FRAMING ERROR (FERR)

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read-only FERR bit is buffered along with the received

data. It is cleared on any Reset.

15.5.3

PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes. It is cleared on any Reset.

15.5.4

IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-

pletion of the Stop bit and detection of the next Start bit,

the RIDLE bit is ‘1’, indicating that the UART is Idle.

15.5.5

RECEIVE BREAK

The receiver will count and expect a certain number of

bit times based on the values programmed in the

PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)

bits.

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is set,

FERR is set, zeros are loaded into the receive FIFO,

interrupts are generated if appropriate and the RIDLE

bit is set.

When the module receives a long break signal and the

receiver has detected the Start bit, the data bits and the

invalid Stop bit (which sets the FERR), the receiver

must wait for a valid Stop bit before looking for the next

Start bit. It cannot assume that the break condition on

the line is the next Start bit.

Break is regarded as a character containing all ‘0’s with

the FERR bit set. The Break character is loaded into

the buffer. No further reception can occur until a Stop bit

is received. Note that RIDLE goes high when the Stop

bit has not yet been received.

15.6

Address Detect Mode

Setting the ADDEN bit (UxSTA<5>) enables this spe-

cial mode in which a 9th bit (URX8) value of ‘1’ identi-

fies the received word as an address, rather than data.

This mode is only applicable for 9-bit data communica-

tion. The URXISEL control bit does not have any

impact on interrupt generation in this mode since an

interrupt (if enabled) will be generated every time the

received word has the 9th bit set.

15.7

Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

To select this mode:

Configure UART for desired mode of operation.

Set LPBACK = 1 to enable Loopback mode.

Enable transmission as defined in Section 15.3

“Transmitting Data”.

15.8

Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximum flexibility in baud rate generation. The Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

BRG = 16-bit value held in UxBRG register

(0 through 65535)

FCY = Instruction Clock Rate (1/TCY)

The baud rate is given by Equation 15-1.

EQUATION 15-1:

BAUD RATE

Therefore, the maximum baud rate possible is:

FCY /16 (if BRG = 0),

and the minimum baud rate possible is:

FCY / (16* 65536).

With a full 16-bit Baud Rate Generator at 30 MIPS

operation, the minimum baud rate achievable is

28.5 bps.

Baud Rate = FCY / (16*(BRG+1))

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