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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F-E/SS датащи(PDF) 175 Page - Microchip Technology |
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PIC16F-E/SS датащи(HTML) 175 Page - Microchip Technology |
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175 / 178 page  © 2007 Microchip Technology Inc. DS40044F-page 173 PIC16F627A/628A/648A Duty Cycle................................................................... 59 Example Frequencies/Resolutions ............................. 59 Period.......................................................................... 58 Set-Up for PWM Operation ......................................... 59 TMR2 to PR2 Match ................................................... 58 Q Q-Clock ............................................................................... 59 Quick-Turnaround-Production (QTP) Devices ...................... 7 R RC Oscillator ....................................................................... 99 RC Oscillator Mode Block Diagram............................................................. 99 Reader Response ............................................................. 170 Registers CCP1CON (CCP Operation)....................................... 55 CMCON (Comparator Configuration).......................... 61 CONFIG (Configuration Word).................................... 96 EECON1 (EEPROM Control Register 1) .................... 90 INTCON (Interrupt Control)......................................... 24 Maps PIC16F627A ................................................. 16, 17 PIC16F628A ................................................. 16, 17 OPTION_REG (Option) .............................................. 23 PCON (Power Control) ............................................... 27 PIE1 (Peripheral Interrupt Enable 1)........................... 25 PIR1 (Peripheral Interrupt Register 1) ........................ 26 Status.......................................................................... 22 T1CON Timer1 Control).............................................. 48 T2CON Timer2 Control).............................................. 53 Reset................................................................................... 99 RETFIE Instruction............................................................ 124 RETLW Instruction ............................................................ 125 RETURN Instruction ......................................................... 125 Revision History ................................................................ 167 RLF Instruction.................................................................. 125 RRF Instruction ................................................................. 126 S Serial Communication Interface (SCI) Module, See USART Serialized Quick-Turnaround-Production (SQTP) Devices ... 7 SLEEP Instruction ............................................................. 126 Software Simulator (MPLAB SIM)..................................... 130 Special Event Trigger. See Compare Special Features of the CPU .............................................. 95 Special Function Registers ................................................. 18 Status Register ................................................................... 22 SUBLW Instruction............................................................ 126 SUBWF Instruction ........................................................... 127 SWAPF Instruction............................................................ 127 T T1CKPS0 bit ....................................................................... 48 T1CKPS1 bit ....................................................................... 48 T1CON Register ................................................................. 48 T1OSCEN bit ...................................................................... 48 T1SYNC bit ......................................................................... 48 T2CKPS0 bit ....................................................................... 53 T2CKPS1 bit ....................................................................... 53 T2CON Register ................................................................. 53 Timer0 Block Diagrams Timer0/WDT ....................................................... 46 External Clock Input.................................................... 45 Interrupt....................................................................... 45 Prescaler .................................................................... 46 Switching Prescaler Assignment ................................ 47 Timer0 Module............................................................ 45 Timer1 Asynchronous Counter Mode ..................................... 50 Capacitor Selection .................................................... 51 External Clock Input ................................................... 49 External Clock Input Timing........................................ 50 Oscillator..................................................................... 51 Prescaler .............................................................. 49, 51 Resetting Timer1 ........................................................ 51 Resetting Timer1 Registers ........................................ 51 Special Event Trigger (CCP) ...................................... 57 Synchronized Counter Mode ...................................... 49 Timer Mode ................................................................ 49 TMR1H ....................................................................... 50 TMR1L ........................................................................ 50 Timer2 Block Diagram ............................................................ 52 Postscaler................................................................... 52 PR2 register................................................................ 52 Prescaler .............................................................. 52, 59 Timer2 Module............................................................ 52 TMR2 output ............................................................... 52 TMR2 to PR2 Match Interrupt..................................... 58 Timing Diagrams Timer0 ...................................................................... 145 Timer1 ...................................................................... 145 USART Asynchronous Receiver...................................... 81 USART Asynchronous Master Transmission ............. 78 USART Asynchronous Reception .............................. 81 USART Synchronous Reception ................................ 87 USART Synchronous Transmission ........................... 85 Timing Diagrams and Specifications ................................ 142 TMR0 Interrupt.................................................................. 108 TMR1CS bit ........................................................................ 48 TMR1ON bit........................................................................ 48 TMR2ON bit........................................................................ 53 TOUTPS0 bit ...................................................................... 53 TOUTPS1 bit ...................................................................... 53 TOUTPS2 bit ...................................................................... 53 TOUTPS3 bit ...................................................................... 53 TRIS Instruction ................................................................ 127 TRISA ................................................................................. 31 TRISB ................................................................................. 36 U Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................. 71 Asynchronous Receiver Setting Up Reception.......................................... 83 Asynchronous Receiver Mode Address Detect ................................................... 83 Block Diagram .................................................... 83 USART Asynchronous Mode ................................................... 77 Asynchronous Receiver.............................................. 80 Asynchronous Reception............................................ 82 Asynchronous Transmission ...................................... 78 Asynchronous Transmitter.......................................... 77 Baud Rate Generator (BRG) ...................................... 73 Block Diagrams Transmit.............................................................. 78 USART Receive ................................................. 80 BRGH bit .................................................................... 73 |
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