DSPIC33FJ12MC02ESS datasheet(175/284 Pages) MICROCHIP

175 / 284 page

Preliminary

DS70265B-page 173

dsPIC33FJ12MC201/202

16.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices can be serial EEPROMs, shift regis-

ters, display drivers, analog-to-digital converters, etc.

The SPI module is compatible with SPI and SIOP from

Motorola®.

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a status

The serial interface consists of 4 pins:

• SDIx (serial data input)

• SDOx (serial data output)

• SCKx (shift clock input or output)

•SSx (active low slave select).

In Master mode operation, SCK is a clock output. In

Slave mode, it is a clock input.

16.1

Interrupts

A series of 8 or 16 clock pulses shift out bits from the

SPIxSR to SDOx pin and simultaneously shift in data

from the SDIx pin. An interrupt is generated when the

transfer is complete and the corresponding interrupt flag

bit (SPI1IF) is set. This interrupt can be disabled through

an interrupt enable bit (SPI1IE).

16.2

Receive Operations

The receive operation is double-buffered. When a

complete byte is received, it is transferred from

SPIxSR to SPIxBUF.

If the receive buffer is full when new data is being

transferred from SPIxSR to SPIxBUF, the module sets

the SPIROV bit, indicating an overflow condition. The

transfer of the data from SPIxSR to SPIxBUF is not

completed, and the new data is lost. The module will

not respond to SCL transitions while SPIROV is ‘1’,

effectively disabling the module until SPIxBUF is read

by user software.

16.3

Transmit Operations

Transmit writes are also double-buffered. The user

application writes to SPIxBUF. When the Master or

Slave transfer is completed, the contents of the shift

transmit data has been written to the buffer register, the

contents of the transmit buffer are moved to SPIxSR.

The received data is thus placed in SPIxBUF and the

transmit data in SPIxSR is ready for the next transfer.

16.4

SPI Setup: Master Mode

To set up the SPI module for the Master mode of

operation:

If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

Write the SPIxIP bits in the respective IPCn

Write the desired settings to the SPIxCON

Clear the SPIROV bit (SPIxSTAT<6>).

Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

Write the data to be transmitted to the SPIxBUF

soon as data is written to the SPIxBUF register.

Note:

This data sheet summarizes the features

of the dsPIC33FJ12MC201/202 devices.

It is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to the

“dsPIC33F Family Reference Manual”.

Please see the Microchip web site

(www.microchip.com)

for

the

latest

dsPIC33F Family Reference Manual

chapters.

Note:

Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register.

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