CC1110-RTR1 datasheet(151/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 151 of 202

Table 40: Flash Lock Protection Bits Definition

Bit

Name

Description

7:5

Reserved, write as 0

Boot Block Lock

Page 0 is write protected

BBLOCK

Page 0 is writeable, unless LSIZE is 000

Lock Size. Sets the size of the upper Flash area which is write

protected. Byte sizes are listed below

000

32K bytes (All pages)

001

16K bytes

010

8K bytes

011

4K bytes

100

2K bytes

101

1K bytes

110

512 bytes

3:1

LSIZE[2:0]

111

0 bytes (no pages)

Debug lock bit

Disable debug commands

DBGLOCK

Enable debug commands

13.14.4 Flash Write Timing

The Flash Controller contains a timing

generator

which

controls

the

timing

sequence of flash write and erase

operations. The timing generator uses the

information set in the Flash Write Timing

internal timing. FWT.FWT[5:0] must be

set to a value according to the currently

selected system clock frequency.

The value set in the FWT.FWT[5:0] shall

be set according to the system clock

frequency by the following equation.

21000 F

FWT

∗

Where F is the system clock frequency.

The initial value held in FWT.FWT[5:0]

after a reset is 0x25 which corresponds to

26 MHz CPU clock frequency.

The FWT values for the possible system

clock frequencies are given in Table 41.

System clock

frequency (MHz)

FWT

0x15

0x2A

Table 41: Flash timing (FWT) values

13.14.5 Flash Controller Registers

The

Flash

Controller

registers

are

described in this section.

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