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AT89C51CC02CA-RATUM датащи(PDF) 134 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM датащи(HTML) 134 Page - ATMEL Corporation |
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134 / 156 page ![]() 134 AT/T89C51CC02 4126J–CAN–05/06 Registers Figure 57. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register Reset Value = 0000 0000b bit addressable 76 54 32 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7EA Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. 5ET2 Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3ET1 Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2EX1 External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1ET0 Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0EX0 External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. |
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