ST7L15 datasheet(127/138 Pages) STMICROELECTRONICS

127 / 138 page

ST7L15, ST7L19

127/138

OPTION BYTES (cont’d)

15.1.1 Flash Option Bytes

The 2 option bytes allow the hardware configura-

tion of the microcontroller to be selected.

OPTION BYTE 0

OPT7 = Reserved (must be set to 0)

OPT6 = Reserved (must be set to 1)

OPT5:4 = CLKSEL Clock Source Selection

When the internal RC oscillator is not selected

(Option OSC = 1), these option bits select the

clock source: Resonator oscillator or external

clock.

Note: When the internal RC oscillator is selected,

the CLKSEL option bits must be kept at their de-

fault value in order to select the 256 clock cycle

delay (see Section 7.5).

OPT 3:2 = SEC[1:0] Sector 0 size definition

These option bits indicate the size of sector 0 ac-

cording to the following table.

OPT1 = FMP_R Readout protection

Readout protection, when selected provides a pro-

tection against program memory content extrac-

tion and against write access to Flash memory.

Erasing the option bytes when the FMP_R option

is selected will cause the whole memory to be

erased first and the device can be reprogrammed.

Refer to the ST7 Flash Programming Reference

Manual and section 4.5 on page 12 for more de-

tails.

0: Readout protection off

1: Readout protection on

OPT 0 = FMP_W Flash write protection

This option indicates if the Flash program memory

is write protected.

Warning: When this option is selected, the pro-

gram memory (and the option bit itself) can never

be erased or programmed again.

0: Write protection off

1: Write protection on

OPTION BYTE 1

OPT7 = PLLx4x8 PLL Factor selection

0: PLLx4

1: PLLx8

OPT 6 = PLLOFF PLL Disable

This option bit enables or disables the PLL.

0: PLL enabled

1: PLL disabled (bypassed)

OPT 5 = Reserved (must be set to 1)

OPT 4 = OSC RC Oscillator Selection

This option bit enables to select the internal RC

oscillator.

0: RC oscillator on

1: RC oscillator off

Note: If the RC oscillator is selected, then to im-

prove clock stability and frequency accuracy, it is

recommended to place a decoupling capacitor,

typically 100nF, between the VDD and VSS pins as

close as possible to the ST7 device.

OPT 3:2 = LVD[1:0] Low Voltage Selection

These option bits enable the voltage detection

block (LVD) with a selected threshold to the LVD.

Clock Source

Port C

CLKSEL

Resonator

Ext. Osc Enabled/

Port C Disabled

External clock

source: CLKIN

on PB4 Ext. Osc Disabled/

Port C Enabled

on PC0

Reserved

Sector 0 Size

SEC1

SEC0

0.5 Kbyte

1Kbyte

2Kbytes

4Kbytes

Configuration

VD1

VD0

LVD Off

LVD High Threshold

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