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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72F324J4TA датащи(PDF) 143 Page - STMicroelectronics |
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ST72F324J4TA датащи(HTML) 143 Page - STMicroelectronics |
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143 / 167 page  ST72324B 143/167 12.13 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes: 1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fADC ADC clock frequency 0.4 2 MHz VAREF Analog reference voltage 0.7*VDD ≤VAREF ≤VDD 3.8 VDD V VAIN Conversion voltage range 1) VSSA VAREF Ilkg Positive input leakage current for analog input -40°C ≤TA≤+85°C ±250 nA +85°C ≤TA≤+125°C ±1 µA Negative input leakage current on ro- bust analog pins VIN<VSS, | IIN |< 400µA on adjacent robust ana- log pin 56 µA RAIN External input impedance see Figure 80 and Figure 812)3)4) k Ω CAIN External capacitor on analog input pF fAIN Variation freq. of analog input signal Hz CADC Internal sample and hold capacitor 12 pF tADC Conversion time (Sample+Hold) fCPU=8MHz, SPEED=0 fADC=2MHz 7.5 µs tADC - No of sample capacitor loading cycles - No. of Hold conversion cycles 4 11 1/fADC 1 |
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