ADE7169ASTF16 datasheet(120/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 120 of 140

multiprocessor network such as RS-485, the 9th bit is set to

indicate that the frame contains the address of the device that

the master would like to communicate with. The devices on the

network are always listening for a packet with the 9th bit set and

are configured such that if the 9th bit is clear, the frame will not

be valid and a receive interrupt will not be generated. If the 9th

bit is set, all of the devices on the network will receive the

address and get a receive character interrupt. The devices will

examine the address and if it matches a device’s preprogrammed

address, the device will configure itself to listen to all incoming

frames, even those with the 9th bit clear. Since the master has

initiated communication with that device, all the following

packets with the 9th bit clear are intended specifically for the

addressed device until another packet with the 9th bit set is

received. If the address does not match, the device will continue

listening for address packets.

To transmit, the 8 data bits must be written into SBUF. The

ninth bit must be written to TB8 in SCON. When transmission

is initiated, the 8 data bits from SBUF are loaded into the

transmit shift register (LSB first). The 9th data bit, held in TB8,

is loaded into the 9th bit position of the transmit shift register.

The transmission starts at the next valid baud rate clock. The

transmit interrupt flag, TI, is set as soon as the transmission has

completed, when the stop bit appears on TxD.

All of the following conditions must be met at the time the final

shift pulse is generated to receive a character:

•

If the extended UART is disabled (EXTEN=0 in the CFG

SFR), RI must be zero to receive a character. This ensures

that the data in SBUF will not be overwritten if the last

received character has not been read.

•

If multiprocessor communication is enabled by setting

SM2, the received 9th bit must be set to receive a character.

This ensures that only frames with the 9th bit set, frames

that contain addresses, generate a receive interrupt.

If any of these conditions are not met, the received frame is

irretrievably lost, and the receive interrupt flag, RI, is not set.

Reception for Mode 2 is similar to that of Mode 1. The 8 data

bytes are input at RxD (LSB first) and loaded onto the receive

shift register. If the received frame has met the above criteria,

the following events occur:

•

The 8 bits in the receive shift register are latched into SBUF.

•

The 9th data bit is latched into RB8 in SCON.

•

The receiver interrupt flag (RI) is set.

Mode 3 (9-Bit UART with Variable Baud Rate)

Mode 3 is selected by setting both SM0 and SM1. In this mode,

the 8051 UART serial port operates in 9-bit mode with a variable

baud rate. The baud rate is set by a timer overflow rate. Timer 1

or Timer 2 can be used to generate baud rates or both timers

can be used simultaneously where one generates the transmit

rate and the other generates the receive rate. There is also a

dedicated timer for baud rate generation, UART Timer, which

has a fractional divisor to precisely generate any baud rate—see

the UART Timer Generated Baud Rates section. The operation

of the 9-bit UART is the same as for Mode 2, but the baud rate

can be varied.

In all four modes, transmission is initiated by any instruction

that uses SBUF as a destination register. Reception is initiated in

Mode 0 when RI = 0 and REN = 1. Reception is initiated in the

other modes by the incoming start bit if REN = 1.

UART BAUD RATE GENERATION

Mode 0 Baud Rate Generation

The baud rate in Mode 0 is fixed:

Mode 0 Baud Rate =

⎟

⎠

⎞

⎜

⎝

⎛

core

Mode 2 Baud Rate Generation

The baud rate in Mode 2 depends on the value of the SMOD bit

in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the

core clock. If SMOD = 1, the baud rate is 1/16 of the core clock:

Mode 2 Baud Rate =

2SMOD

× Fcore

Modes 1 and 3 Baud Rate Generation

The baud rates in Modes 1 and 3 are determined by the overflow

rate of the timer generating the baud rate: either Timer 1 or

Timer 2 or the dedicated baud rate generator, UART Timer,

which has an integer and fractional divisor.

Timer 1 Generated Baud Rates

When Timer 1 is used as the baud rate generator, the baud rates

in Modes 1 and 3 are determined by the Timer 1 overflow rate

and the value of SMOD as follows:

Modes 1 and 3 Baud Rate =

2SMOD

× Timer 1 Overflow Rate

The Timer 1 interrupt should be disabled in this application.

The timer itself can be configured for either timer or counter

operation, and in any of its three running modes. In the most

typical application, it is configured for timer operation in

autoreload mode (high nibble of TMOD = 0010 binary). In that

case, the baud rate is given by the formula

Modes 1 and 3 Baud Rate =

)

256

(

core

SMOD

−

Timer 2 Generated Baud Rates

Baud rates can also be generated by using Timer 2. Using Timer 2

is similar to using Timer 1 in that the timer must overflow 16

times before a bit is transmitted or received. Because Timer 2

has a 16-bit autoreload mode, a wider range of baud rates is

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