ADE7169F16 datasheet(105/140 Pages) AD

105 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 105 of 140

These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins.

Table 96. Timer/Counter 2 Control SFR (T2CON, 0xC8)

Bit

Location

Bit

Addr.

Bit

Name

Default

Value

Description

0xCF

TF2

Timer 2 Overflow Flag.

Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1.

Cleared by user software.

0xCE

EXF2

Timer 2 External Flag.

Set by hardware when either a capture or reload is caused by a negative transition on T2EX

and EXEN2 = 1.

Cleared by user software.

0xCD

RCLK

Receive Clock Enable Bit.

Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in

serial port Modes 1 and 3.

Cleared by the user to enable Timer 1 overflow to be used for the receive clock.

0xCC

TCLK

Transmit Clock Enable Bit.

Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in

serial port Modes 1 and 3.

Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.

0xCB

EXEN2

Timer 2 External Enable Flag.

Set by the user to enable a capture or reload to occur as a result of a negative transition on

T2EX if Timer 2 is not being used to clock the serial port.

Cleared by the user for Timer 2 to ignore events at T2EX.

0xCA

TR2

Timer 2 Start/Stop Control Bit.

Set by the user to start Timer 2.

Cleared by the user to stop Timer 2.

0xC9

CNT2

Timer 2 Timer or Counter Function Select Bit.

Set by the user to select the counter function (input from external T2 pin).

Cleared by the user to select the timer function (input from on-chip core clock).

0xC8

CAP2

Timer 2 Capture/Reload Select Bit.

Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.

Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at

T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is

forced to autoreload on Timer 2 overflow.

Table 97. Timer 0 High byte SFR (TH0, 0x8C)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-0

TH0

Timer 0 Data high byte

Table 98. Timer 0 Low byte SFR (TL0, 0x8A)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-0

TL0

Timer 0 Data high byte

Table 99. Timer 1 High byte SFR (TH1, 0x8D)

Bit Location

Bit Mnemonic

Default

Value

Description

7-0

TH1

Timer 1 Data high byte

Table 100. Timer 1 Low byte SFR (TL1, 0x8B)

Bit Location

Bit Mnemonic

Default

Value

Description

7-0

TL1

Timer 1 Data high byte

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