AM68AX datasheet(138/251 Pages) TI

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7.10.3.3 Clock Timing

Tables and figures provided in this section define timing requirements and switching characteristics for clock

signals.

Table 7-19. Clock Timng Requiements

see Figure 7-21

NO.

MIN

MAX UNIT

CLK1

tc(EXT_REFCLK1)

Cycle time minimum, EXT_REFCLK1

CLK2

tw(EXT_REFCLK1H)

Pulse Duration minimum, EXT_REFCLK1 high

E*0.45(1)

E*0.55(1)

CLK3

tw(EXT_REFCLK1L)

Pulse Duration minimum, EXT_REFCLK1 low

E*0.45(1)

E*0.55(1)

(1)

E = EXT_REFCLK1 cycle time.

Figure 7-21. Clock Timing Requirements

Table 7-20. Clock Switching Characteristics

see Figure 7-22

NO.

PARAMETER

MIN

MAX UNIT

CLK4

tc(SYSCLKOUT0)

Cycle time minimum,SYSCLKOUT0

CLK5

tw(SYSCLKOUT0H)

Pulse Duration minimum, SYSCLKOUT0 high

A*0.4(1)

A*0.6(1)

CLK6

tw(SYSCLKOUT0L)

Pulse Duration minimum, SYSCLKOUT0 low

A*0.4(1)

A*0.6(1)

CLK7

tc(OBSCLK0)

Cycle time minimum, OBSCLK0

CLK8

tw(OBSCLK0H)

Pulse Duration minimum, OBSCLK0 high

B*0.4(2)

B*0.6(2)

CLK9

tw(OBSCLK0L)

Pulse Duration minimum,OBSCLK0 low

B*0.4(2)

B*0.6(2)

CLK10 tc(CLKOUT0)

Cycle time minimum, CLKOUT0

CLK11 tw(CLKOUT0H)

Pulse Duration minimum, CLKOUT0 high

C*0.4(3)

C*0.6(3)

CLK12 tw(CLKOUT0L)

Pulse Duration minimum,CLKOUT0 low

C*0.4(3)

C*0.6(3)

(1)

A = SYSCLKOUT0 cycle time.

(2)

B = OBSCLK0 cycle time.

(3)

C = CLKOUT0 cycle time.

Figure 7-22. Clock Switching Characteristics

AM68A

SPRSP91 – FEBRUARY 2023

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